1. Field of the Invention
The present invention generally relates to a system bus control system in a multi-processor system and, more particularly, is directed to a system bus utilization request system, an inter-unit communication system in a multi-processor system employing a system bus of a time split transfer system and a multi-processor system having a shared memory.
2. Description of the Related Art
A multi-processor system has recently been used to construct a control unit of a computer, an electronic switching system and the like. In this system, a plurality of processors are interconnected via a single system bus to share hardware and software resources, thereby improving throughput, expandability and reliability.
Furthermore, a bus arbiter for controlling and arbitrating a utilization right of a system bus is accessed, to enable a plurality of processors to transmit and receive data between them and other processors via the single system bus and a memory to be interconnected to the system bus.
FIG. 1 is a schematic block diagram showing an example of an arrangement of a conventional multi-processor system having such a bus arbiter.
Referring to FIG. 1, a plurality of CPU (central processing unit) boards (processor units) CPU.sub.0 to CPU.sub.N, memory boards (memory units) CM.sub.0 to CM.sub.N and a bus arbiter (BA) 12 are interconnected to a system bus 11. The bus arbiter 12 is adapted to control and arbitrate the bus utilization right of each board.
FIGS. 2A and 2B show arrangements of each CPU board CPUi (i=0, 1, . . . , N) and memory board CMj, respectively. As shown in FIG. 2A, each CPU board CPUi is composed of a microprocessor (.mu.P) 15, a control register (CTLREG) 16 and a bus interface (BIF) 14 and, as shown in FIG. 2B, each memory board CMj is composed of a RAM (random access memory) 18, a RAM controller 17 and the bus interface 14. The bus interface 14 controls the interconnection between a local bus 13 and the system bus 11 within the board.
A data transfer system called a time split system is known for a system bus in the multi-processor system. In this system, a command transfer cycle and an answer transfer cycle are separated.
FIG. 3 is a diagram showing an example of a timing in which a command and an answer are transmitted in the system bus of the time split transfer system. This example illustrates a case where a CPU board CPUi reads data D stored in a memory address A from a memory CMj.
CPUi of a CPU board transmits a bus request signal RQi to the bus arbiter 12 before transmitting a command C and a memory address A to memory CMj. When receiving a transfer permission signal GRi from the arbiter 12, the CPU board CPUi transmits the command C and the memory address A to the memory board CMj through the system bus 11. When receiving the command C and the memory address A through the system bus 11, the memory board CMj transmits the transfer request signal RQi to the bus arbiter 12 in order to transmit an answer AN and the data D stored in the memory address A to the CPU board CPUi. When receiving the transfer permission signal GRj from the bus arbiter 12, the memory board CMj transmits the answer AN and the data D to the CPUi via the system bus 11.
As described above, in the system bus of the conventional time split transfer system, when each CPU board transmits the command C or the answer AN, each CPU board must transmit the bus request signal to the bus arbiter 12 individually.
FIG. 4 is a block circuit diagram of the bus interface 14 provided within each CPU board CPUi and memory board CMj.
As shown in FIG. 4, the bus interface 14 includes a transmission FIFO 21 of a first in first-out system which stores transmission data and a reception FIFO 22 of a first-in first-out system which stores reception data. Buffers 23, 25 and buffers 24, 26 are respectively provided between these FIFOs 21, 22, the local bus 13 and the system bus 11.
Transmission data are temporarily stored in buffer 23 and then in the transmission FIFO 21. Transmission data sequentially read out of the FIFO 21 are temporarily stored in the buffer 24 and then transmitted to the system bus 11.
Reception data are stored in buffer 26 and then stored in the reception FIFO 22. Reception data sequentially read out of the reception FIFO 22 are temporarily stored in buffer 25 and transmitted to the local bus 13.
Reception control units 27, 30 and transmission control units 28, 29 are adapted to control the writing and reading of these buffers 23 to 26 when data are transmitted and received. Transmission FIFO control unit 31 and a reception FIFO control unit 32 are adapted to instruct a write address and a read address of the transmission FIFO 21 and the reception FIFO 22, respectively.
FIG. 5 is a block diagram showing a specific arrangement of the transmission FIFO control unit 31 which is shown by the hatched portion in FIG. 4.
As shown in FIG. 5, an input address unit 33 is a circuit which instructs the write address of the transmission FIFO 21 and outputs an address, which is sequentially incremented by one, to the transmission FIFO 21 in accordance with a signal supplied thereto through an OR gate 34 from the reception control unit 27 or from the transmission control unit 29. Of the write addresses output from the input address unit 33, a breakpoint address of transmission data row is stored in a queue buffer 35. An output of the OR gate 34 is supplied to the transmission FIFO 21 as a data write signal WE and data are written into the transmission FIFO 21 in response to the data write signal WE.
The output address unit 36 is a circuit which instructs a read address of the transmission FIFO 21 and outputs addresses, which are sequentially incremented by one, to the transmission FIFO 21 in accordance with the read signal from the transmission control unit 28. The read address of the output address unit 36 and the breakpoint address of the transmission data row of the queue buffer 35 are compared by a comparator 37, and the reading of data in the transmission FIFO 21 is continued until the two addresses coincide.
An input completion display FF 38 is a flip-flop which is set by a signal from the reception control unit 27 or from the transmission control unit 29 via the OR gate 39 upon data transfer, and an output completion display FF 40 is a flip-flop which is set when the data transfer is finished.
A comparator 41 compares the outputs of flip-flops 38 and 40 to determine whether a command C or an answer AN transfer request signal RQ should be transmitted from the transmission control unit 28 or not.
For example, when the input completion display FF 38 is set and the output completion display FF 40 is reset, data to be transferred remain so the comparator 41 detects that the outputs of FFs 38 and 40 are not coincident. Thus, the transmission control unit 28 outputs the command C or the answer AN transfer request signal RQ.
In this time split transfer system, during the idle period other than that in which the command C or the answer AN is output, the system bus 11 is opened to each board. However, it is frequently observed that the system bus 11 is occupied between particular boards to perform data transfer, which is called a lock transfer.
FIG. 6 is a diagram showing examples of the command C format and the answer AN used in the lock transfer. As shown in FIG. 6, the command C is composed of a data field indicating destination, a data field indicating the unit from which data is transmitted, a data field indicating the kind of data and a data field indicating the data transfer amount. Also, the answer AN is composed of a data field indicating destination, a data field indicating the unit from which data is transmitted, a data field indicating the kind of data and a data field for the answer code.
FIG. 7 is a diagram used to explain the operation of the system upon lock transfer. The bus arbiter (BA) 12 is arranged such that, when receiving the lock transfer signal, the bus arbiter 12 recognizes the destination board from the destination data in the command C to receive only the transfer request from the destination board so as to transfer the answer AN.
FIG. 8 is a circuit block diagram showing a main portion of the bus arbiter. Reference will be made to this figure in explaining the bus arbiter's function of receiving only the transfer request from the destination board upon a lock transfer.
Referring to FIG. 8, destination data in the command C is stored in a destination buffer 51 and the destination data is decoded by a decoder (DEC) 52. The decoded data is thereby output to an OR gate group 54.
The command and the lock transfer signal are respectively input to a C/AN recognition circuit 56 and a lock recognition circuit 57. Outputs from these recognition circuits 56 and 57 are supplied through an AND gate 58 or an inverter 59 to a set terminal S or a reset terminal R of an RS flip-flop (RS-FF) 60. A Q output of the RS-FF 60 is supplied to one input terminal of OR gates 54-i (i=0, 1, . . . , N) of the OR gate group 54. When the lock transfer signal is input to the RS-FF 60 and the Q output of the RS-FF 60 goes low level, one input terminal of OR gates 54-i of the OR gate group 54 all become low level and only the other input terminal of OR gate 54-i corresponding to the destination data stored in the destination buffer 51 becomes high level. Thus, of AND gate group 61, only AND gate 61-i corresponding to the destination data is opened to permit the transfer request signal from the destination data to be input to an arbitrating circuit 62.
The arbitrating circuit 62 issues a transfer permission signal GR.sub.1 corresponding to the transfer request signal output from the AND gate group 61 at its AND gate 61-i corresponding to the destination data. Upon lock transfer, only the transfer request signal from the designated destination data stored in the destination buffer 51 becomes active and is input to the arbitrating circuit 62 as described above, with the result that the transfer permission signal GRi (i=0, 1, . . . , N) can be transmitted only to the designated destination board.
In the data transfer system of the time split system, the bus arbiter controls the transfer request signals of commands and answers from the respective boards interconnected to the system bus and sequentially issues the transfer permission signal in the order of boards having highest priority.
When the CPU board CPUi transfers the command and awaits the answer from the memory board CMj, if the command transfer request signal is output from a CPU board CPUn having higher priority, then the transfer permission signal is issued to the CPU board CPUn and the transfer of answer from the memory board CMj to the CPU board CPUi is awaited.
In general, the local bus 13 within the CPU board CPUi is of the interlock type such that the local bus 13 is held until it receives the answer from the destination board. Consequently, when the time split transfer system is utilized as the data transfer system of the system bus, there arises a problem that, until the answer is returned, other units within the board cannot utilize the local bus 13. Further, when the lock transfer system is employed as the data transfer system of the system bus, the system bus can be occupied only by a particular board so that the answer waiting time can be reduced. However, the circuit must be constructed such that the bus arbiter 12 identifies the destination board so that it receives only the transfer request from it and refuses transfer requests from other boards. Thus, a complicated circuit arrangement cannot be avoided.
The time split transfer system is effective for decreasing a system bus occupying ratio and for increasing a system bus utilization ratio in a particular CPU board (hereinafter referred to as a processor unit) in the multi-processor system.
In a multi-processor system employing a system bus which is not based on the time split transfer system, the occupying ratio in which the system bus is occupied by a particular processor unit is increased because such a processor unit exclusively occupies the system bus when it is allowed to use it. In the time split transfer system, however, such restriction does not occur because a plurality of processor units utilize the system bus in a time sharing manner, allowing other processor units to sequentially utilize the system bus without awaiting the answer to the access request. Therefore, respective processor units can execute different processings via the single system bus.
In either of the above two bus systems, an apparatus (hereinafter referred to as a unit) may be requested to be connected to the system bus so as to input and output data in a data width different from the bus width inherent in the system bus in accordance with the expansion of system function.
An example of an arrangement of such system is represented in the schematic block diagram in FIG. 9. FIG. 9 shows the arrangement of the multi-processor system which employs a system bus that does not use time split transfer system.
In this system, a system bus 100 includes a bus width information line 106 in addition to a data bus 102 and an address bus 104, and a plurality of units 110-1, 110-2, . . . , 110-N are connected to the system bus 100.
A data transfer operation of this system will be described below with reference to a timing chart of FIG. 10.
Referring to FIG. 9, when a first unit 110-j (j=1, 2, . . . , N; i=j) is accessed via the bus width information line 106 by a second unit 110-i (i=1, 2, . . . , N) of the plurality of units 110-1, 110-2, . . . , 110-N, data and addresses are transferred through the data bus 102 and the address bus 104. Bus width information is also transferred through the bus width information line 106. When the reception unit 110-j receives the bus width information, the reception unit 110-j can identify the bus width of transferred data and can correctly transmit and receive data. Incidentally, the bus width information line 106 is occupied similarly to the data bus 102 and the address bus 104 (see (A), (B) and (C) of FIG. 10).
However, if the system shown in FIG. 9 is constructed by using the system bus of the time split transfer system, as shown in FIG. 11, the plurality of units 110-1, 110-2, . . . , 110-N are connected to a system bus 103 which is formed of an address bus and a data bus.
A data transfer operation between the units in the system shown in FIG. 11 employing the time split transfer system, system bus will be described next with a timing chart forming FIG. 12.
In the time split system, the single system bus is utilized in a time sharing fashion as described above. According to this time split system, before an answer (see answer AN1 in FIG. 12) is returned to a first unit for a command and an address (see command C1 and address A in FIG. 12) transmitted from the first unit, a command and an address (see command C2 and address B in FIG. 12) from a second unit are transmitted so that the bus width information cannot be held until the answer is returned to the first unit, unlike in the conventional bus system illustrated in FIG. 9. As a result, the transmission and reception of data having a data width different from the bus width of the system bus 103 (see FIG. 11) cannot be performed. There is then the problem that, in the conventional time split system, the unit having a data width different from the bus width of the system bus cannot be utilized in the system.
A sharing memory multi-processor system is used for sharing a hardware resource in the multi-processor system. In this system, a plurality of processors share one memory in use. To cope with control forms which presumably become more and more complicated, a wide variety of control must be realized by an input and output unit which is made common to respective processors interconnected to a system bus.
FIG. 13 is a block diagram showing an example of a system arrangement of a conventional sharing memory multi-processor system.
In FIG. 13, a shared memory (CM) 201, respective processor units (PU.sub.1 to PU.sub.3) 210-1 to 210-3 and an input and output unit (IOU) 220 are interconnected to a system bus 230. The shared memory 201 and the processor units 210-1 to 210-3 have bus interface circuits (BIF) 201a and 211a to 213a to which individual identifiers (IDs) are assigned so that they can recognize their own access by determining whether the identifier (ID) transmitted on the system bus 230 is equal to the identifiers (IDs) assigned to their bus interface circuits.
An image of a memory area which can be accessed by respective processor units 210-1 to 210-3 is represented in FIG. 14. In this example, half the memory space is utilized by a shared memory area Mc and the remaining half is utilized by local memory area Ml of respective processor units 210-1 to 210-3.
To access such memory space, a boundary address for indicating a boundary of addresses and identifiers (IDs) for the shared memory 201 are set between the bus interface circuits (BIF) 201a and 211a to 213a so that, when addresses of internal buses 211b to 213b provided within respective processor units 210-1 to 210-3 access the shared memory area Mc, as shown in FIG. 15 the shared memory 201 can be accessed via the system bus 230 by utilizing the identifier of the shared memory 201 set in a shared memory identifier register 216a provided within an external bus interface unit 216 within the bus interface circuits 211a to 213a of respective processor units 210-1 to 210-3. Thus, the local memory area Ml can be independently utilized only within respective processor units 210-1 to 210-3. In other words, respective processor units 210-1 to 210-3 cannot access the local memory area Ml of another processor unit. More specifically, when a comparator 218 detects that an internal bus address B is smaller than an address A previously set in a boundary register 217 (A&gt;B), the external bus interface unit 216 shown in FIG. 15 is enabled, and if A&lt;B, then the external bus interface unit 216 determines that the access is the access to the local memory area Ml so that the external bus interface unit 216 is not enabled.
A bus interface circuit 220a of the input and output unit (IOU) 220 shared by respective processor units 210-1 to 210-3 interconnected to the system bus 230 is also arranged as shown in FIG. 15. In this circuit, the access to the shared memory area Mc can be effected, but the local memory area Ml of each of the processor units 210-1 to 210-3 cannot be accessed. Accordingly, in the conventional shared memory multi-processor system, although the direct memory access (DMA) transfer of the shared memory area Mc can be carried out, the local memory area Ml of each of the processor units 210-1 to 210-3 cannot be accessed so that the input and output unit 230 cannot perform the DMA transfer to the local memory area Ml of each of the processor units 210-1 to 210-3 by the input and output apparatus 220b. This causes the problem that complex control cannot be achieved.